// 4-bit ALU using fulladd4 
// addition, subtraction, AND, OR
//

module alu4(alu_out, c_out, a, b, func);
output [3:0] alu_out;
tri [3:0] alu_out;
output c_out;
input [3:0] a, b;
input [1:0] func;

wire [3:0] add_out, and_out, or_out, b_in;
wire and_en, or_en, f1n, f0n;

fulladd4 fa4(add_out, c_out, a, b_in, func[0]);

and(and_out[3], a[3], b[3]);
and(and_out[2], a[2], b[2]);
and(and_out[1], a[1], b[1]);
and(and_out[0], a[0], b[0]);

or(or_out[3], a[3], b[3]);
or(or_out[2], a[2], b[2]);
or(or_out[1], a[1], b[1]);
or(or_out[0], a[0], b[0]);

bufif1(alu_out[3], add_out[3], f1n);
bufif1(alu_out[2], add_out[2], f1n);
bufif1(alu_out[1], add_out[1], f1n);
bufif1(alu_out[0], add_out[0], f1n);

bufif1(alu_out[3], and_out[3], and_en);
bufif1(alu_out[2], and_out[2], and_en);
bufif1(alu_out[1], and_out[1], and_en);
bufif1(alu_out[0], and_out[0], and_en);

bufif1(alu_out[3], or_out[3], or_en);
bufif1(alu_out[2], or_out[2], or_en);
bufif1(alu_out[1], or_out[1], or_en);
bufif1(alu_out[0], or_out[0], or_en);

xor(b_in[3], b[3], func[0]);
xor(b_in[2], b[2], func[0]);
xor(b_in[1], b[1], func[0]);
xor(b_in[0], b[0], func[0]);

not(f1n, func[1]);
not(f0n, func[0]);
and(and_en, func[1], f0n);
and(or_en, func[1], func[0]);

endmodule

// Define the stimulus (top level module)
module stimulus;

// Set up variables
reg [3:0] A, B;
reg [1:0] FUNC;
wire [3:0] SUM;
wire C_OUT;

// Instantiate the 4-bit full adder. call it FA1_4
alu4 ALU4(SUM, C_OUT, A, B, FUNC);


// Setup the monitoring for the signal values
initial
begin
  $monitor($time,": A= %b, B= %b, FUNC = %b, SUM= %b\n", 
  A, B, FUNC, SUM);
end

// Stimulate inputs
initial
begin
	A = 5; B = 3; FUNC = 0;

	#50 FUNC = 1;

	// Here, you need to write Verilog statements to test function the other functions for different inputs.

end	

endmodule

//
// all the rest are taken from the textbook
//
// Define a 1-bit full adder
module fulladd(sum, c_out, a, b, c_in);

// I/O port declarations
output sum, c_out;
input a, b, c_in;

// Internal nets
wire s1, c1, c2;

// Instantiate logic gate primitives

xor  (s1, a, b);
and (c1, a, b);

xor (sum, s1, c_in);
and (c2, s1, c_in);

or  (c_out, c2, c1);

endmodule


// Define a 4-bit full adder 
module fulladd4(sum, c_out, a, b, c_in); 
 
// I/O port declarations
output [3:0] sum;
output c_out;
input[3:0] a, b;
input c_in;
 
// Internal nets 
wire c1, c2, c3; 
 
// Instantiate four 1-bit full adders.
fulladd fa0(sum[0], c1, a[0], b[0], c_in);
fulladd fa1(sum[1], c2, a[1], b[1], c1);
fulladd fa2(sum[2], c3, a[2], b[2], c2);
fulladd fa3(sum[3], c_out, a[3], b[3], c3);

endmodule