Catalog Description: Digital design
methodology and techniques; control and timing; machine organization,
instruction sequencing and data for flow control; control unit design;
and techniques.
|
Chapter |
Topics |
Homework |
| 3 | Combinational Logic Design Chapter 3 I Chapter 3 II |
3-15, 3-29,
3-39, 3-44, 3-46, 6-4, 6-6 Due 2/1/08 |
| 4 | Arithmetic Functions and HDL Chapter 4 Verilog HDL i Verilog HDL ii |
4-4 (b) and
(d), 4-16, 4-31, 4-33, 4-34 Due 2/14/08 |
| 5 | Sequential Circuits Chapter 5 I Chapter 5 II |
5-7, 5-8, 5-9,
5-13 Due 2/20/08 |
| 7 | Register Design Chapter 7I Chapter 7II |
7-11, 7-20 Due 2/27 |
| 8 | Memory Chapter 8 |
8-1, 8-3, 8-9, 8-11 Due 3/17 |
| 9 |
Computer Design
|
9-4, 9-5, 9-9 (a, b, d, g), 9-11, 9-17 Due 3-28 (PLEASE NO LATE HOMEWORK) |
| 10 |
Intro to Computer Architecture Chapter10 ISA, Single-Cycle Computer Chapter 11, Pipelined RISC CPU Performance FINAL REVIEW NOTES |
Last Homework (pipelining) Due 4-25 (PLEASE NO LATE HOMEWORK) |
Exams
Exam 1 is scheduled for 2-27-08 (chapters 3, 4, 5, 7)Exam 2 is scheduled for 4-9-08 (chapters 8 & 9)