//Refer to the circuit diagram in the lab handout

//4-bit binary counter; counts 0 - F with RESET and ENABLE
//Positive Edge-Triggered D Flip-Flop with Reset

module registers_4bit(CLK, RESET, D, Q);
  input CLK, RESET, D;
  output Q;
  reg state;

  assign Q = state;

  always @(posedge CLK or posedge RESET)
  begin
    if (RESET)
      state <=0;
    else 
      state <=D;
    end
    endmodule

    module Counter_4bit(CLK, Reset, EN, Q, CO);

    input CLK, Reset, EN;
    output [3:0] Q;
    output CO;
    wire[3:0]Q;

    wire[3:0]C, D_in;
 
//assign AND gates and CO
assign
    C[0]=EN,
    C[1]=C[0]&Q[0],
     .
     .
     .


//assign XOR gates
assign 
    D_in[0] = C[0] ^ Q[0],
    D_in[1] = C[1] ^ Q[1],
    .
    .
    .

registers_4bit
    g1(CLK, Reset, D_in[0], Q[0]),
    .
    .
    .

endmodule