Costa P. Gerousis,  Ph.D
Associate Professor

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TEACHING - Fall 09

HONOR100: Honor Seminar (material on Blackboard)
PHYS151: Intermediate Physics I (material on Blackboard)
CPEN214: Digital Logic Design
CPSC330: Computer Organizations and Design (material on Blackboard)

TEACHING - Spring 09

CPEN214: Digital Logic Design
CPEN315: Digital and Computer System Design
PHYS152: Intermediate Physics II  (material on Blackboard)

TEACHING - Fall 08

ULLC100: First Year Seminar
PHYS151: Intermediate Physics I
PHYS201: General Physics I
CPSC330: Computer Organizations and Design

CPSC110: Introduction to Computing - WebCT (SP06)
PHYS202: General Physics II (SP06, S07)
PHYS202L: General Physics II Lab (S06)
PHYS201: General Physics I  (F04)
PHYS151: Intermediate Physics (F05)
CPEN499: Computer Engineering Capstone Project (SP04)
CPEN214: Digital Logic Design (F03-F07)
CPEN315: Digital Systems (S04, S07, S08)
CPEN315L: Digital Systems Lab (SP04, SP07, SP08)
ULLC100: FYS, Evolution of Wired Life (F06, F07)
CPSC330: Computer Organizations (F04-F07)

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OFFICE HOURS - Fall 2009

            M:  12:00 pm – 1:30 pm

            W:  1:00 pm – 2:30 pm

            R:   1:00 pm – 2:00 pm

            F:   1:00 pm – 2:00 pm                                                                                                           

And by appointment only.

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RESEARCH

Nanotechnology , Single-Electron Device, Nanoelectronic Cellular Neural Networks (CNNs), Hybrid  MOS-SET circuits.

Several emerging nanoscale device replacements for bulk-effect semiconductor transistor have been suggested to overcome the problems accompanied by scaling.  Among the new devices is the single electron tunneling (SET) transistor that offers attractive features such as reduced dimensions, high integration density, and low power consumption.  My research investigates the use of SETs for potential application in future high density and low power networks.

Selected Publications

• A. Riedl, D. Wang, C. Gerousis, R. Flores, D. Doughty, “A Robotics Platform for Capstone Projects in Computer Engineering and Computer Science”, Proceedings of the International Conference on Frontiers in Education: Computer Science and Computer Engineering (FECS '09) hosted by 2009 World Congress in Computer Science, Computer Engineering & Applications (WorldComp 2009), Las Vegas, July 13-16, 2009, pp. 217-222.

• C. Gerousis and A. Grepiotis, “Design and Simulation of Programmable Nanoelectronic Single-Electron Digital Circuits,” Proceedings of the IASTED International Conference on Circuits and Systems, pp. 49-54, 2008.

• C. Gerousis and D. Ball, “Single-Electron Tunneling Circuits for Image Processing Applications,” Proceedings of the 2008 International Conference on Computer Design (CDES'08), pp. 139-144, 2008.

• C. Gerousis, “Tunneling Circuits and Cellular Architectures,” Proceedings of the IASTED International Conference on Circuits and Systems, pp. 116-121, 2008.

• C. Gerousis and A. Grepiotis, “Programmable Logic Arrays in Single-Electron Transistor Technology,” Proceedings of the IEEE International Conference on Signals and Electroni Systems (ICSES), 2008. 

• S. M. Goodnick, C. Gerousis, R. Archibald, R. A. Kiehl, and F. Hoppenstaedt, “Cellular Single-Electron Transistor Circuits and Architectures.” Conference on Nanoscale Devices and System Integration, April 5, 2005.

• C. Gerousis, S. M. Goodnick, W. Porod, “Nanoelectronic Single-electron Transistor Circuits and Architectures,” International Journal of Circuit Theory and Applications, vol. 32, pp. 323-538, 2004.

• C. Gerousis, S.M. Goodnick,  IEEE Si Nanoelectronics Workshop,  "Single-Electron Transistor Circuits and Cellular Nonlinear Networks", June 13-14, 2004, Honolulu, Hawaii.

• C. Gerousis, S.M. Goodnick, W. Porod,  2^nd International Workshop on Quantum Dots for Quantum Computing and Classical Size Effect Circuit (IWQDDC-2), University of Notre Dame, Indiana, 2003

• C. Gerousis and S. M. Goodnick “Simulation of Single-Electron Tunneling Circuits,” Physica Status Solidi, vol. 233, no. 1, 2002.

• C. Gerousis, S. M. Goodnick, W. Porod, A. I. Csurgay, “High-Speed and Low-Power Cellular Neural Networks Using Single-Electron Tunneling Technology.” Proceedings of IEEE International Symposium on Circuits and Systems, Part 2, II-45-48, 2002.

• D. K. Ferry, M. Koury, C. Gerousis, M. J. Rack, A. Gunther, S. M. Goodnick, “Single-electron charging effects in Si MOS devices,” Physica E, vol. 9, pp. 69-75, 2001.