-------------------------------------------------------------------------------- --------------------------------- DesignSteps ---------------------------------- -------------------------------------------------------------------------------- ---------- This procedure describes the steps to go from a completed ----------- ---------- schematic design, to a layout, including Dracula checks. ----------- -------------------------------------------------------------------------------- 7/19/95 --- for Opus 4.3.3.26 using CMOSX with cmosx.tf Open schematic from Library Browser Tools -> Floorplan/Schematics Floorplan -> Hierarchy Browser OK Utilities -> Environment Change Default Global Signal Names Use Existing Global Names = OFF Library = current library Global Power Signal Name = VDD! Global Ground Signal Name = VSS! OK Hierarch -> Generate Physical Hierarchy This create an autoLayout view. Edit top cell view autoLayout. Tools -> Floorplan/P&R -> Cell Ensemble OSW = Instance Floorplan -> Reinitialize... OK Floorplan -> IO place... IO Distribution Mode = even Fixed Die = off Min. IO-to-Core Distance = 100 (or whatever) OK *** Manually move pads to their desirable locations (or): *** Floorplan -> Floorplan File -> Read... (existing IO file) *** Floorplan -> Floorplan File -> Write... (existing IO file) Place -> IO Commands -> Add Corners... Glue Cell Library Name = CamPads Glue Cell Master Name = Z08CRNR Glue Cell Master View = abstract OK *** Manually move macro cells to a location inside core (or): *** Floorplan -> Floorplan File -> Read... (existing Macro Cell file) *** Floorplan -> Floorplan File -> Write... (existing Macro Cell file) *** Before placement the default region can be modified to adjust *** the number of standard cell rows (in region properties). Place -> Automatic... Method = both Insert Feedthru = off Options: Initial: Fast Placement = off Vertical Wire Weight = 1 OK Improve: Improve Placer Mode = normal Initial Temperature = 0 Jumper Search Range = 4 Vertical Wire Weight = 1 Fix Placed IO Position = on OK OK Place -> IO Commands -> Justify... IO Align Style = free Align Feature = supplyPins IO to Core Spacing = 100 (or whatever) IO to IO Spacing = 0 Placement Snap Grid = 0.1 Shift IO Frame to Origin = on OK Select all instances. Place -> Snap To Grid... Selected Cells = on Placement Snap Grid = 0.1 OK Analyze -> Check -> Cell Overlap Cell Bounding Box = partial overlap OK Design -> Save As... View Name = placed OK Route -> Channels -> Display Cutlines... Initial Cut = horizontal / vertical Cut With Barriers = off OK Route -> Channels -> Remove Cutlines Route -> Channels -> Create... Initial Cut = (best looking choice) Channel Name = Channels Cut With Barriers = off OSW = Net Edit -> Select -> By Name... Name Pattern = VDD! OK Route -> Modify Net -> Split Net OK Edit -> Select -> By Name... Name Pattern = VSS! OK Route -> Modify Net -> Split Net OK OSW = nothing Route -> Modify Net -> Modify Net Properties... Net Names = VDD!Int Edit Net Priority = 115 Edit Net Width = 20 Edit Net Separation = 3 Edit Net Type = supply OK Route -> Modify Net -> Modify Net Properties... Net Names = VSS!Int Edit Net Priority = 114 Edit Net Width = 20 Edit Net Separation = 3 Edit Net Type = ground OK Route -> Global Route -> Automatic... Method = auto Options Automatic: Expansion Mode = fast Congestion Cost = off Use Stub Routing = off OK Apply Method = optimize Options Optimizer: Speed = fast / medium / slow Step Factor = 1 (range: 0.1 to 1.0) Mirror Cells = on Remove Unused Feedthru = off OK OK *** The length of time spent global routing is adjusted with the *** Speed and Step Factor. *** The quickest route uses fast speed with a 0.1 step factor. *** The longest route uses slow speed with a 1.0 step factor. *** Slow speed generates better results but with a time penalty. Route -> Global Route -> Interactive Global Route... Initialize Net... Net Name = VDD!Int OK Select all applicable VDD net points. Connect Set Exit Net... Fix Net Global Route Topology = on OK OK Initialize Net... Net Name = VSS!Int OK Select all applicable VSS net points. Connect Set Exit Net... Fix Net Global Route Topology = on OK OK Done Design -> Save As... View Name = global OK OSW = Instance Select channels that you want to modify routing layers in. Route -> Detail Route -> Switch Layer... Primary Layer = metal2 Secondary Layer = metal1 / metal3 OK Route -> Detail Route -> Automatic... Compaction Mode = automatic Contact Style = offCentered Add Conditional Via = off Routing Layers = 3 Layers Options Compact: Placement Snap Grid = 0.05 Rectangular IO Frame = on Symbolic Routing = off Stagger Exit Contacts = on Contour Channel Exits = on Align Formal Pins = off Channel Boundary Extending = to instance blockages OK OK Route -> Detail Route -> Explode Channels OK Floorplan -> Replace View... Instances To Work On = all To View Name = layout OK Design -> Save As... View Name = layout OK Design -> Discard Edits Yes (discard edits) Window -> Close Open and edit layout. Tools -> Layout Edit cellview properties by typing shift q Property = on Delete designPlanCE of viewSubType OK Window -> Close Yes (save changes) Open and edit layout. Edit -> Search... Search for contact Add Criteria contact type == via Apply Select All Cancel Edit -> Other -> Flatten... Flatten Mode = one level Flatten PCells = on Preserve Pins = off OK Edit -> Search... Search for contact Add Criteria contact type == via2 Apply Select All Cancel Edit -> Other -> Flatten... Flatten Mode = one level Flatten PCells = on Preserve Pins = off OK Design -> Save Window -> Close *** The following steps fix metal notches that occur near vias *** that are sometimes created during cell ensemble routing. Technology File -> Compile Technology... Library Name = current layout library Technology File = ~/techfile/FillNotches.tf Action = load OK Edit layout Verify -> DRC... OK Design -> Save Window -> Close *** Close library and discard technology file changes. *** The loss of diva drc rules will result otherwise. Create a stream directory. Create a netlist directory. Create a dracula directory. Create DRC directory. Create LVS directory. Copy layermap.drc and layermap.lvs to the stream directory. Copy cmosxDRC from Dracula/cmosx to DRC directory. Copy cmosxLOGLVS and cmosxLVS from Dracula/cmosx to LVS directory. *** Two stream files need to be generated. The difference is the *** RESID layer that is included in the lvs stream file for *** performing lvs checks with resistors. Translators -> Physical -> Stream Out... Template File = ~/current directory/stream directory/template.drc Run Directory = ~/current directory/stream directory Library Name = working library name Top Cell Name = top cell name View Name = layout Output = Stream DB Output File = stream.drc Scale UU/DBU = 0.00100000 Units = micron Layer Map Table = layermap.drc Options: Case Sensitivity = preserve Error Message File = log.drc OK Copy stream.drc as a link to the DRC directory. Open command tool and change to the DRC directory. Run the cmosxDRC script and answer the following: Enter primary structure name: Enter stream file name: Run in background? {y,n} *** The drc summary will be found in printf.drc. Inquery may also be used *** to graphically view drc errors if any. The errors found by dracula drc *** need to be corrected by having an integrated circuit designer or *** graduate student edit the layout. A violations file is created that *** shows each check and the number of errors found, which can be used *** as a quick reference. Translators -> Physical -> Stream Out... Template File = ~/current directory/stream directory/template.lvs Run Directory = ~/current directory/stream directory Library Name = working library name Top Cell Name = top cell name View Name = layout Output = Stream DB Output File = stream.lvs Scale UU/DBU = 0.00100000 Units = micron Layer Map Table = layermap.lvs Options: Case Sensitivity = preserve Error Message File = log.lvs OK For CDL Out to work, the .simrc file should have the following: ; for cdl ; substitute proper directories in place of those in cdlSimLibPath cdlSimViewList = '( "cdl" "schematic" "cmos.sch" "gate.sch" "symbol") cdlSimStopList = '("cdl") cdlSimLibPath = "~/Pads /usr/cds0/mosis_kit1/roads ~/Cam4 /usr/cds0/mosis_kit1/cmosx/opus_libs/ms080_libs /usr/cds0/mosis_kit1/opus_libs/ms080_libs " simCdlPwrNetList = '("VDD!") simCdlGndNetList = '("VSS!") hnlCDLNMOSBulkNetName="VSS!" hnlCDLPMOSBulkNetName="VDD!" Translators -> Netlist -> CDL Out... Top Cell Name = top cell name View Name = schematic Library Name = working library name Output File = cdl.des Run Directory = ~/current directory/netlist directory Resistor Threshold Value = 10 Check Resistors = value OK Copy stream.lvs as a link to the LVS directory. Copy cdl.des to LVS directory. Create CORRESPONDENCE file in LVS directory with correspondence nodes for pads. Open command tool and change to LVS directory. Run cmosxLOGLVS and answer the following: Enter CDL filename: Enter top-level structure name: Is this the first time running runLOGLVS on this CDL netlist? (y or n)? *** If yes to the above question an EQUIVALENT *** statement is added to the cdl netlist. Run cmosxLVS and answer the following: Enter primary structure name: Enter stream file name: Run in background? {y,n} *** The lvs summary will be found in printf.lvs. Inquery may also be used *** to graphically view lvs errors if any (very slow). The errors found by *** dracula lvs need to be corrected by having an integrated circuit designer *** or graduate student edit the layout. *** Once the design passes Dracula, the file can be prepared *** for sending / retrieving. Copy stream.drc file to a new directory and rename it filename.gds. uuencode filename.gds filename > filename.uugds checksum filename.uugds Layout-checksum goes on the submission request.