CAM Architecture
The architecture resembles a conventional CAM with address decode logic
feeding the array and encoding logic to determine pattern match addresses.
What is not conventional, is that each byte matches independently and
stores a match or no match status. This match status is
then fed into a majority function which determines if a
word match occurs. The threshold of the majority function can be externally
controlled. One, two, three or four byte matches may cause a word match.
Word matches are then encoded and output. The final CAM chip will be
256x32. It will use bidectional data (32-bits) and address lines (8-bits).
The chip operation is determined by a 3-bit opcode. Other signals include:
chip select, byte selects, mode bits, output ready and reset.