CAM 4 Specifications
A complete change in technology to 3 layer metal, 0.8 micron.
Results in a more dense, less area design.
schematic capture -> verilog simulation -> floorplan place & route -> final layout
transistor design -> spice simulation -> transistor layout
Memory Size: 16 words x 4 x 8 bits
Physical Size: 2.97mm x 3.03mm -> 9.00 sq mm
Technology: 0.8 micron
3 layer metal
cmosx library
Transistor Count: 13710
Pin Count: Data 32
Address 4
Opcode 3
Clock 2
Enable 4
Mode 2
Reset 1
Chip Select 1
Output Ready 1
VDD 6
VSS 6
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Total 62