CAM 5 Specifications
3 layer metal, 0.8 micron, CMOSX Design Rules.
schematic capture -> verilog simulation -> floorplan place & route -> final layout
transistor design -> spice simulation -> transistor layout
Memory Size: 64 words x 4 x 8 bits
Physical Size: 4.6mm x 3.7mm
Technology: 0.8 micron
3 layer metal
cmosx library
Transistor Count: ~180,000
Pin Count: Data 32
Address 6
Opcode 3
Clock 2
Enable 4
Mode 2
Reset 1
Chip Select 1
Output Ready 1
VDD 8
VSS 8
-------------------
Total 68 (We used MOSIS's 84 pin PGA)