CMOS POWER DISTRIBUTION STUDY

The following description specifies the work to be performed over the the period from July 1996 through July 97. The work will be performed by CNU professors and students and be associated with developing techniques for designing reliable power distribution networks for standard cell CMOS VLSI designs. The goal of this study is to develop a general power distribution design methodology that could be applied to technologies used by DoD and integrated into DoD's CMOS design methodology. This study is designed to address the major issues in power distribution network design. We see the major issues as being:
  1. Electromigration (High current densities causing increased resistance or failure of metal conductors),
  2. Voltage Drop (due to resistance in power lines),
  3. Ground Bounce (due to inductance in ground buses).
The above issues will be addressed in the following tasks:
  1. Physical Modeling of Distribution Interconnects,
  2. Electrical Modeling of CMOS Power Distribution Networks.

Physical Modeling of Distribution Interconnects

This research will be performed to gain insight and understanding about the physical structures used to distribute power throughout CMOS standard cell circuits. The research will focus on typical structures and geometries used in routing standard cells. Current density analysis will be performed to determine reliability thresholds which could be employed to reduce or effectively eliminate electromigration effects. These thresholds will be used in developing strategies for reliable power distribution networks.

Electrical Modeling of CMOS Power Distribution Networks

This research will focus on developing models for typical power distribution networks used in CMOS-based standard cells designs. Issues of voltage drop and ground bounce will be studied to determine how to manage these problems effectively. Voltage drop along power distribution buses reduces the noise margin for standard cells increasing failure due to noise related problem. Inductive effects in power distribution networks may also cause noise problems due to LdI/dt EMF generated by transient current during circuit clock transitions. Appropriate models for resistance, capacitance and inductance of interconnects will be determined as well as models for standard cells. Simulations will be performed to determine network response and validity of the different power distribution methodologies.

For more info email, rhodson@pcs.cnu.edu